Support and development for the project “Place&Route design support for ASICs and SoCs in nanometer

The work to be performed by contractor is the place and route for digital design parts up to top level based on chip specification, Verilog netlists, SDC synthesis constraint data and physical synthesis floorplans including layout extraction and physical design verification (DRC, LVS). Such work includes definition of the implementation flow and a sufficient documentation of the design implementation.In addition there is work on the Interposer layer in different technologies (silicon or organic) for Chiplet designs to be performed.

•All design and implementation work shall be executed in cooperation betweenIIS and contractor by using Cadence (P&R) and Mentor (DRC, LVS) design software on IISservers via remote or on-site access. •The work shall be executed partially remote, partially on site based on projects needs •Cadence design software, technology libraries, standard cella, memory and GPI/O modelaccess as well as IP access will be made available on IIS servers •Mentor Calibre physical design verification software access will be made available on IISservers

•All design and implementation work shall be carefully documented and reportedbetween project manager and contractor in a montly progress report •The use of Cadence Innovus, Quantus, 2.5 D tools (P&R) and Mentor Calibre (DRC, LVS) software is mandatory, as well as knowledge about the Cadence AI tools. •All milestones at the end of each project with contractor’s responsibility will be pre-reviewed by contractor on its own responsibility. The review documentation will bereviewed by IIS and contractor in meetings via internet or at Fraunhofer IIS Erlangen. •Acceptance criteria: Design flow, implementation documentation and design data baseresults are available on IIS servers, the correct functionality of the layouted designs hasbeen successfully shown in review meetings and meet the expected results of thespecification and project management.

Find more Informations in the Tender Specification