Awarding of contracts for Complex SoC digital backend design

Within the STX project a high performance computing application class specific accelerator chip for very complex multi-dimensional stencil and tensor calculations will be developed in 12 nm FinFET silicon technology. In BCDC platform SoCs for industrial use cases are developed and in TrEB SoCs with security and safety functionalities both in 22 FDSOI technology. For the chip implementation a digital backend design expert is requested to execute floorplanning, timing and power analysis, power routing, top level and hierarchical block level place&route and layout verification. Therefore, a view (max. 3 per year) on-demand-meetings might be performed at the Fraunhofer Institute for Integrated Circuits IIS in Erlangen-Tennenlohe. Furthermore, flexibility of working hours is required in order to be able to react promptly to urgent adjustments, as well as the willingness to undertake national and international business trips, if necessary. Details can be found in "B.1_Lot1_Tender_description

In the TrEB, AHSI and BCDC projects specific multi core compute and peripheral SoCs and chiplets for reusable partitioned systems in industrial and research use cases will be developed in 12 nm FinFET and 22 nm FDSOI silicon technology. A digital backend design expert for floorplanning, timing and power optimization and hierarchical block level layout and verification is requested. Therefore, a view (max. 3 per year) on-demand-meetings might be performed at the Fraunhofer Institute for Integrated Circuits IIS in Erlangen-Tennenlohe. Furthermore, flexibility of working hours is required in order to be able to react promptly to urgent adjustments, as well as the willingness to undertake national and international business trips, if necessary. Details can be found in "B.2_Lot2_Tender_description